Recently, a number of processors have been proposed for improving the performance of an instruction by simultaneously processing the instruction sequences of a plurality of threads by hardware (hereinafter the processors are referred to as “multi-thread processors”).
It may be necessary for the multi-thread processors to be internally provided with an architecture register (for example, a program counter, a general purpose register, etc.) for each thread. As a result, the amount of hardware of a multi-thread processor is larger than the amount of hardware of a processor for processing the instruction sequence of a single thread (hereinafter referred to as a “single thread processor”). The increasing amount of hardware causes a larger number of occurrences of hardware errors with the development of micro fabrication technique.
Accordingly, there is a demand for a processor capable of continuing processing without reducing the performance of the processor although a hardware error occurs.
In this respect, for example, the patent document 1 discloses a multi-thread processor for improving the entire process efficiency by dynamically realizing the performance required for each instruction sequence.
On the other hand, a multi-thread processor does not constantly execute the instruction sequences of a plurality of threads, but may execute only the instruction sequence of a single thread when, for example, it may be necessary to process only the instruction sequence of a single thread, or when other threads may not be processed until a certain thread is completely processed on the condition of software in the case where a lock release or synchronization between threads is awaited.
In this respect, for example, the patent document 2 discloses a method of changing the internal control of hardware by switching between a multi-thread mode and a single thread mode by executing an instruction to switch a thread mode.
The patent document 3 discloses an SMT (simultaneous multi-thread processing) system for optimization in any of the multi-thread mode and the single thread mode.
When a multi-thread processor supports a thread mode switch instruction to switch between valid and invalid states of a thread, it is possible to change from the single thread mode to the multi-thread mode. However, a thread that has newly entered a valid state is to start the execution from a specific address (for example, system reset interrupt handler etc.). Therefore, it is not suitable for a use in which the thread processing is temporarily suspended for a short time waiting for a lock release or for waiting for synchronization between threads.
In addition, when the above-mentioned thread mode switch instruction is used, there is no means for placing a thread in the valid state from software if all threads are placed in the invalid state. Therefore, an exception notification is transmitted to the software. Accordingly, all threads may not be simultaneously placed in the invalid state, and it may be necessary for the software to be certainly aware of the existence of other threads when the thread mode switch instruction is used.
In this connection, for example, the patent document 4 discloses a controlling method by executing an instruction to temporarily suspend the process of a thread, discarding a part of the resources dividable among threads that have been assigned to the thread, and reassigning them to another thread.
However, in this controlling method, only the assignment of the resources dividable among threads is changed. For example, the instruction processing controlling method may not be changed. Therefore, an instruction processing efficiency is degraded.
Patent Document 1: Japanese Laid-open Patent Publication No. 10-124316
Patent Document 2: Specification of U.S. Pat. No. 7,155,600
Patent Document 3: Japanese Laid-open Patent Publication No. 2004-326752
Patent Document 4: National Publication of International Patent Application No. 2005-514698